Summary: Appears in 35th IEEE/ACM International Symposium on Computer Architecture (ISCA), Beijing, China, June 2008.
Globally-Synchronized Frames for
Guaranteed Quality-of-Service in On-Chip Networks
Jae W. Lee, Man Cheuk Ng
Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology
Cambridge, MA 02139
{leejw, mcn02}@csail.mit.edu
Krste Asanovi´c
Computer Science Division, EECS Department
University of California at Berkeley
Berkeley, CA 94720-1776
krste@eecs.berkeley.edu
Abstract
Future chip multiprocessors (CMPs) may have hundreds
to thousands of threads competing to access shared re-
sources, and will require quality-of-service (QoS) support
to improve system utilization. Although there has been
significant work in QoS support within resources such as
caches and memory controllers, there has been less atten-

Source: Asanoviæ, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Enright Jerger, Natalie - Department of Electrical and Computer Engineering, University of Toronto
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

Collections: Computer Technologies and Information Sciences; Engineering