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1126 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 6, JUNE 2007 Microprocessor Verification via
 

Summary: 1126 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 6, JUNE 2007
Microprocessor Verification via
Feedback-Adjusted Markov Models
Ilya Wagner, Student Member, IEEE, Valeria Bertacco, Member, IEEE,
and Todd Austin, Member, IEEE
Abstract--The challenge of verifying a modern microprocessor
design is an overwhelming one: Increasingly complex microarchi-
tectures combined with heavy time-to-market pressure have forced
microprocessor vendors to employ immense verification teams in
the hope of finding the most critical bugs in a timely manner.
Unfortunately, too often, size does not seem to matter in verifica-
tion, as design schedules continue to slip and microprocessors find
their way to the marketplace with design errors. In this paper, we
describe a novel closed-loop simulation-based approach to hard-
ware verification and present a tool called StressTest that uses our
methods to locate hard-to-find corner-case design bugs and perfor-
mance problems. StressTest is based on a Markov-model-driven
random instruction generator with activity monitors. The model
is generated from the user-specified template files and is used to
generate the instructions sent to the design under test (DUT). In

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan
Bertacco, Valeria - Department of Electrical Engineering and Computer Science, University of Michigan

 

Collections: Computer Technologies and Information Sciences; Engineering