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Reliability Effects of Process and Thread Redundancy on Chip Multiprocessors Dakai Zhu Hakan Aydin
 

Summary: Reliability Effects of Process and Thread Redundancy on Chip Multiprocessors
Dakai Zhu Hakan Aydin
Department of Computer Science Department of Computer Science
University of Texas at San Antonio George Mason University
San Antonio, TX, 78249 Fairfax, VA 22030
dzhu@cs.utsa.edu aydin@cs.gmu.edu
I. INTRODUCTION AND BACKGROUND
The phenomenal performance gains in successive computer
technologies have been obtained at the cost of drastic increases
in power densities. This fact promoted energy to a first-class sys-
tem resource, and energy-aware computing has recently become
a major research area. At the same time, with the continued
scaling of CMOS technologies and reduced design margins,
VLSI circuits have become more susceptible to transient faults
that are induced by energic particles (e.g., neutrons and alpha
particles), and today, reliability concerns are pronounced more
strongly for all computing systems [7]. The widely popular
energy management technique, dynamic voltage scaling (DVS)
has been shown to have direct and negative effects on the
system reliability due to the increased transient fault rates

  

Source: Aydin, Hakan - Department of Computer Science, George Mason University
Zhu, Dakai - Department of Computer Science, University of Texas at San Antonio

 

Collections: Computer Technologies and Information Sciences; Engineering