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CLOCK SKEW ON DRAM/LOGIC MERGED TECHNOLOGY BASED SYSTEMS
 

Summary: CLOCK SKEW ON DRAM/LOGIC MERGED TECHNOLOGY
BASED SYSTEMS
Yong-Bin Kim* Tom Chen**
*Engineering Systems Lab. MS-55, Hewlett Packard Co. Fort Collins, CO 80525
ybk@hpesybk.fc.hp.com
**Department of Electrical Engineering, Colorado State Univ. Fort Collins, CO 80523
chenelongs.lance.colostate.edu
ABSTRACT
This paper describes the clock skew estimations
considering all the possible clock skew factors on
DRAM/Logic merged systems. The clock skew dif-
ference between standard logic chip and DRAM/Logic
merged chi s has been estimated as 521 s for 4x4 cm2
die size. TRe relationship between clocf skew and die
size on DRAM/Logic merged systems has been ob-
tained along with the maximum operating clock fre-
quency assuming clock skew can take up to 15%of the
total clock cycle on such a large chip.
1 INTRODUCTION
It has been sug ested that DRAM component

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering