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Sieve: An XML-Based Structural Verilog Rules Submitted to the Department of Electrical Engineering and Computer
 

Summary: Sieve: An XML-Based Structural Verilog Rules
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by
Tina Cheng
Submitted to the Department of Electrical Engineering and Computer
Science
in partial fulfillment of the requirements for the degree of
Master of Engineering in Electrical Engineering and Computer Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
September 2003
c Tina Cheng, MMIII. All rights reserved.
The author hereby grants to MIT permission to reproduce and
distribute publicly paper and electronic copies of this thesis document
in whole or in part.
Author .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Department of Electrical Engineering and Computer Science
August 22, 2003
Certified by. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Krste Asanovi┤c

  

Source: AsanoviŠ, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

 

Collections: Computer Technologies and Information Sciences