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SCALABLE TEST GENERATORS FOR HIGH-SPEED DATAPATH CIRCUITS
 

Summary: 1
SCALABLE TEST GENERATORS FOR HIGH-SPEED
DATAPATH CIRCUITS
1
Hussain Al-Asaad , John P. Hayes , and Brian T. Murray
Advanced Computer Architecture Laboratory
Department of Electrical Engineering and Computer Science
The University of Michigan
1301 Beal Avenue, Ann Arbor, MI 48109-2122
Electrical and Electronics Department
General Motors R&D Center
30500 Mound Road, Warren, MI 48090-9055
ABSTRACT
This paper explores the design of efficient test sets and test-pattern generators for on-
line BIST. The target applications are high-performance, scalable datapath circuits for
which fast and complete fault coverage is required. Because of the presence of carry-
lookahead, most existing BIST methods are unsuitable for these applications. High-level
models are used to identify potential test sets for a small version of the circuit to be tested.
Then a regular test set is extracted and a test generator TG is designed to meet the
following goals: scalability, small test set size, full fault coverage, and very low hardware

  

Source: Al-Asaad, Hussain - Department of Electrical and Computer Engineering, University of California, Davis

 

Collections: Computer Technologies and Information Sciences