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Summary: Abstract - Dynamic burn-in testing is an integral component
of any test plan that seeks to produce reliable integrated circuits.
Despite its importance in ensuring the reliability of semiconduc-
tors, burn-in has been a major contributor to overall test cost
and turnaround time. In this work we discuss the application of
advanced Boolean satisfiability (SAT) techniques to generate a
set of vectors or input stimuli that increases the nodal activity in
the circuit and hence the elevation of its temperature. The vec-
tors are designed to uniformly stress all parts of the circuit. Ad-
ditionally, we present a SAT-based methodology where weak
nodes can selectively be targeted for high switching activity in an
effort to detect potential failures. Finally, SAT-based solvers are
compared against generic Integer Linear Programming (ILP)
solvers when handling the vector generation problem.
Keywords - Testing, Power, Vector Generation, Integer Linear
Programming, Boolean Satisfiability.
I. INTRODUCTION
All integrated circuits that pass production tests are not
identical. When put to actual use, some will fail very quickly
while others will function for a long time. Burn-in ensures re-
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