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Summary: 1
Abstract -- With operational faults becoming
the dominant cause of failure modes in modern
VLSI, widespread deployment of on-line test
technology has become crucial. In this paper,
we present a non-concurrent on-line testing
technique via scan chains. We discuss the
modifications needed in the design so that it
can be tested on-line using our technique. We
demonstrate our technique on a case study of
a pipelined 8x8 multiply and accumulate unit.
The case study shows that our technique is
characterized by high error coverage, moder-
ate hardware overhead, and negligible time
redundancy.
INTRODUCTION
As the ratio of validation/test engineers to design
engineers approaching 3 to 1, the verification and
testing of the design of a computer chip is becom-
ing the most significant part in the chip's overall
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