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CAN. J. ELECT. COMPUT. ENG., VOL. 27, NO. 4, OCTOBER 2002 A High Performance Low Power System-on-Chip Platform
 

Summary: CAN. J. ELECT. COMPUT. ENG., VOL. 27, NO. 4, OCTOBER 2002
1
A High Performance Low Power System-on-Chip Platform
Architecture
A.T. Erdogan1
, T. Arslan1,2
and W.-C. Lo2
1
University of Edinburgh,
Department of Electronics & Electrical Engineering,
Edinburgh EH9 3JL, Scotland, United Kingdom.
2
Institute for System Level Integration, The ALBA Campus,
Livingston, EH64 7BH, Scotland, United Kingdom.
Abstract: This paper describes a System-on-Chip platform architecture for low power high performance
Digital Signal Processing intensive applications. The platform is based on the AMBA SoC bus
protocol and incorporates a novel interfacing scheme which utilises the bus hierarchy within
AMBA in order to allow single and multiple high performance DSP Intellectual Property cores
to be integrated to the SoC platform. The paper describes the overall SoC platform architecture
and the integration scheme, providing results for area usage and power consumption of the

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering