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Summary: Design and Evaluation of Hybrid Fault-Detection Systems
George A. Reis Jonathan Chang Neil Vachharajani
Ram Rangan David I. August
Departments of Electrical Engineering and Computer Science
Princeton University
Princeton, NJ 08540
{gareis,jcone,nvachhar,ram,august}@princeton.edu
Shubhendu S. Mukherjee
FACT Group
Intel Massachusetts
Hudson, MA 01749
shubu.mukherjee@intel.com
Abstract
As chip densities and clock rates increase, processors
are becoming more susceptible to transient faults that can
affect program correctness. Up to now, system design-
ers have primarily considered hardware-only and software-
only fault-detection mechanisms to identify and mitigate
the deleterious effects of transient faults. These two fault-
detection systems, however, are extremes in the design
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