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An All-Digital Phase-Locked Loop with Fast Acquisition and Low Jitter
 

Summary: An All-Digital Phase-Locked Loop with Fast
Acquisition and Low Jitter
JUN ZHAO
Department of Electrical and Computer Engineering
Northeastern University
Boston, USA
jzhao@ece.neu.edu
Yong-Bin Kim
Department of Electrical and Computer Engineering
Northeastern University
Boston, USA
ybk@ece.neu.edu
Abstract-- An all-digital phase-locked loop that achieves fast
acquisition and low jitter was developed for high-speed clock
generation. By employing a time-to-digital converter (TDC), the
frequency difference is precisely measured and converted to the
control word of the digital oscillator. Using this feature, the
ADPLL has a faster lock-in time than previous digital phase-
locked loops. The ADPLL was implemented using a 0.9V 32nm
practical transistor model (PTM). The simulation results show

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering