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Recently, a new Dynamic Voltage Scaling (DVS) scheme has been proposed that increases energy efficiency
 

Summary: Abstract
Recently, a new Dynamic Voltage Scaling (DVS)
scheme has been proposed that increases energy efficiency
significantly by allowing the processor to operate at or
slightly below the minimum supply voltage even if occa-
sional errors result. To determine which technique can
reliably and efficiently detect such failures, it is necessary
to understand the manner in which digital designs fail at
critical voltages. In this paper, we report hardware mea-
surements of the failure modes of a multiplier circuit under
voltage scaling. We show that even at small error rates, it
is necessary to deal with multiple errors where bits are
flipped from both 0 to 1 and 1 to 0. Intra- and inter-die
variations make the exact nature of these flips unpredict-
able. This suggests that conventional single and unidirec-
tional error detectors will not work. We conclude that the
most suitable solution is a simple delay-error tolerant flip-
flop that detects and corrects errors by double sampling
signals.
1. Introduction

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan

 

Collections: Engineering; Computer Technologies and Information Sciences