Home

About

Advanced Search

Browse by Discipline

Scientific Societies

E-print Alerts

Add E-prints

E-print Network
FAQHELPSITE MAPCONTACT US


  Advanced Search  

 
A Novel Technique to Minimize Standby Leakage Power in Nanoscale CMOS VLSI
 

Summary: A Novel Technique to Minimize Standby Leakage
Power in Nanoscale CMOS VLSI
HeungJun Jeon and Yong-Bin Kim
Department of Electrical and Computer Engineering
Northeastern University
Boston, MA, USA
hjeon@ece.neu.edu and ybk@ece.neu.edu
MinSu Choi
Department of Electrical and Computer Engineering
Missouri University of Science & Technology
Rolla, MO, USA
choim@mst.edu
Abstract-- This paper proposes a novel approach to minimize
leakage currents in CMOS circuits during the off-state (or
standby mode, sleep mode) by applying the optimal reverse body
bias to the substrate (body or bulk) to increase the threshold
voltage of transistors. The optimal bias point is determined by
comparing the sub-threshold current (ISUB) and band-to-band
current (IBTBT) simultaneously. The proposed circuit was
simulated in HSPICE using 32nm bulk CMOS technology and

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering