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Appears in Kool Chips Workshop, 33rd International Symposium on Microarchitecture, Monterey, CA, December 2000 Highly-Associative Caches for Low-Power Processors
 

Summary: Appears in Kool Chips Workshop, 33rd International Symposium on Microarchitecture, Monterey, CA, December 2000
Highly-Associative Caches for Low-Power Processors
Michael Zhang and Krste Asanovi┤c
MIT Laboratory for Computer Science, Cambridge, MA 02139
frzhang|krsteg@lcs.mit.edu
1 Introduction
Since caches consume a significant fraction of total pro-
cessor energy, e.g., 43% for StrongARM-1 [8], many stud-
ies have investigated energy-efficient cache designs [1, 5,
12, 13, 14, 15, 18]. However, none of these design stud-
ies have considered using content-addressable-memory
(CAM) tags in highly-associative caches. This is partic-
ularly surprising given that the leading commercial low-
power processors over the last decade have all employed
CAM-tag caches. For example, the ARM3 with 4 KBytes
of 64-way set-associative CAM-tag cache was released in
1989 [9] and the new Intel XScale processor employs 64-
way set-associative CAM tags. Publications which de-
scribe processors with CAM-tag caches [8, 9, 11, 16] in-
clude some discussion of the reasons for choosing CAM

  

Source: AsanoviŠ, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

 

Collections: Computer Technologies and Information Sciences