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Summary: MICROARCHITECTURE MODELING FOR
DESIGN-SPACE EXPLORATION
MANISH VACHHARAJANI
A DISSERTATION
PRESENTED TO THE FACULTY
OF PRINCETON UNIVERSITY
IN CANDIDACY FOR THE DEGREE
OF DOCTOR OF PHILOSOPHY
RECOMMENDED FOR ACCEPTANCE
BY THE DEPARTMENT OF
ELECTRICAL ENGINEERING
NOVEMBER 2004
c Copyright by Manish Vachharajani, 2004.
All Rights Reserved
Abstract
To identify the best processor designs, designers explore a vast design space. To assess
the quality of candidate designs, designers construct and use simulators. Unfortunately,
simulator construction is a bottleneck in this design-space exploration because existing
simulator construction methodologies lead to long simulator development times. This bot-
tleneck limits exploration to a small set of designs, potentially diminishing quality of the
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