Summary: 0018-9162/97/$10.00 © 1997 IEEE September 1997 75
Scalable Processors in
he importance of an efficient memory system is
increasing as fabrication processes scale down,
yielding faster processors and larger memories.
This trend widens the processor-memory gap.
Not long ago, off-chip main memory was able
to supply the CPU with data at an adequate rate. Today,
with processor performance increasing at a rate of about
60 percent per year and memory latency improving by
just 7 percent per year,1
it takes dozens of cycles for data
to travel between the CPU and main memory.
Designers are investing vast amounts of chip
resources to bridge this gap. An increasing fraction of
the area budget within microprocessor chips is devoted
to static RAM (SRAM) caches. For instance, almost