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A Power-Aware Algorithm for the Design of Reconfigurable Hardware during High Level Placement
 

Summary: A Power-Aware Algorithm for the Design of Reconfigurable Hardware
during High Level Placement
Wing On Fung1
School of Electronics and Engineering1,
University of Edinburgh, King's Buildings,
Mayfield Road, Edinburgh, EH9 3JL, UK
wing.fung@ed.ac.uk
Tughrul Arslan1,2
Institute for System Level Integration2,
The Alba Centre, Alba Campus,
Livingston, EH54 7EG, UK
tughrul.arslan@ed.ac.uk
Abstract
The popularity of reconfigurable logic devices and
portable hardware demands ever increasingly power
saving schemes for low power designs. This paper
looks at the CAD design process of reconfigurable
devices and presents a novel method to gain power
savings during the placement stage of the CAD flow.
The proposed system modeled the number of switches

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering