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Electrical and Optical On-Chip Interconnects in Scaled Microprocessors Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David Albonesi, Philippe M. Fauchet, and Eby G. Friedman
 

Summary: Electrical and Optical On-Chip Interconnects in Scaled Microprocessors
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David Albonesi, Philippe M. Fauchet, and Eby G. Friedman
Department of Electrical and Computer Engineering
University of Rochester, Rochester, New York, 14627
Department of Electrical and Computer Engineering
Cornell University, Ithaca, New York, 14853
Abstract-- Interconnect has become a primary bottleneck in inte-
grated circuit design. As CMOS technology is scaled, it will become
increasingly difficult for conventional copper interconnect to satisfy
the design requirements of delay, power, bandwidth, and noise. On-
chip optical interconnect is therefore being considered as a potential
substitute for electrical interconnect. Based on predictions of optical
device development, electrical and optical interconnects are compared
for various design criteria. The critical dimensions beyond which optical
interconnect becomes advantageous over electrical interconnect at the 22
nm technology node are approximately one tenth of the chip edge length.
I. INTRODUCTION
In deep submicrometer VLSI technologies, interconnect plays an
increasingly important role. Multiple design criteria are considered
in interconnect design, such as delay, power, bandwidth, and noise.

  

Source: Albonesi, David H. - Computer Systems Laboratory, Cornell University

 

Collections: Computer Technologies and Information Sciences