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A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency Bo Zhai, Leyla Nazhandali, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand,
 

Summary: A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency
Bo Zhai, Leyla Nazhandali, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand,
Sanjay Pant, David Blaauw and Todd Austin
University of Michigan, Ann Arbor, MI
Abstract
A 2.6pJ/Inst subthreshold sensor processor designed for energy
efficiency has been fabricated. A two-stage micro-architecture was
implemented to mitigate the impact of process variation in
subthreshold operation. Careful library cell selection and robust
SRAM design enabled fully functional operation from 1.2V to
200mV. We analyze the variation in frequency and optimal voltage
and evaluate the need for adaptive control. The processor reaches
maximum energy efficiency at 360mV, consuming 2.6pJ/Inst at
833kHz. The minimum energy consumption of the core marks a 10X
improvement over previous sensor processors at the same MIPS.
1. Introduction
Subthreshold circuit operation is a compelling method for ultra-
low power sensor applications. In previous work [1], we
demonstrated the existence of a so-called minimum energy voltage
(Vmin) where CMOS logic reaches maximum energy efficiency per

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan

 

Collections: Engineering; Computer Technologies and Information Sciences