Summary: Optimizing Designs Containing Black Boxes
The University of Texas at Austin
Tempus Fugit Inc.
We are concerned with optimizing gate-level netlists containing "black boxes", i.e., components
whose functionality is not available to the optimization tool. We establish a notion of equivalence
for gate-level netlists containing black boxes, and prove that it is sound and complete. We show
that conventional approaches to optimizing such netlists fail to fully exploit the don't care flexi-
bility available for synthesis. Based on our new notion of equivalence, we introduce a procedure
which computes the complete don't care set. Experiments indicate that our procedure can achieve
more minimization than conventional synthesis.
Categories and Subject Descriptors: B.6.3 [Logic Design]: Design aids--Automatic synthesis;
D.2.4 [Software Engineering]: Software/Program verification--Formal methods
General Terms: Algorithms, Design, Verification
Additional Key Words and Phrases: Hierarchical logic synthesis, Don't cares, IP-based design