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Efficient Verification of the PCI Local Bus using Boolean Satisfiability

Summary: IWLS'00
Page 1
Efficient Verification of the PCI Local Bus using
Boolean Satisfiability
Fadi A. Aloul and Karem A. Sakallah
Department of Electrical Engineering and Computer Science
University of Michigan
AnnArbor, MI 48109-2122
{faloul, karem}@eecs.umich.edu
Abstract: The purpose of this paper is to study the application of Boolean Satisfiability to the
verification of the PCI Local Bus. The novel feature of this approach is the generation of several
propositional formulas that describe the specification of the bus system. The formulas are tested
using a powerful SAT solver and the bus is verified for errors. The SAT-based approach has sev-
eral important advantages over conventional BDD-based approaches such as achieving high
speed testing. To demonstrate how our method works, we have modeled the PCI Local Bus and
verified several properties.
1 Introduction
Recent developments in semiconductor technology have made possible the integration of over 10 mil-
lion transistors on a single chip. A related practice which is evolving to avoid designing systems from
scratch is the use of predefined logic blocks referred to as Intellectual Property Components (IP cores)


Source: Aloul, Fadi - Department of Computer Engineering, American University of Sharjah


Collections: Engineering