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VHDL Course Hands-on exercise session 2
 

Summary: ­ 1 ­
VHDL Course
Hands-on exercise session 2
A) Objectives
To develop and execute relatively simple VHDL models, in order to improve understanding of:
- VHDL environment
- sequential statements
- delays
- component instantiation
- assertions
B) Modeling entity specification
It is required to develop a behavioral model of a D-type flip-flop. The schematic symbol is given by
Figure 1.
DX3U is a LSSD master-slave D-type flip-flop with 3 MUXes. Its inputs are: normal data (D0, D1
and D2) and control data (C1 and C2). The outputs are Q and QB. The inputs are clocked in the input
section when CK1 is low.
This cell is a Level Sensitive Scan Design (LSSD) function clocked by the two active-low non-
overlapping clocks, CK1 for the input section and CK2 for the output section. When the scan mode control
(SM) is high, scan data (SD) is clocked in. All functions for this cell are synchronous. The function table of
DX3U is represented by table 1. Qi designates the internal value which follows the selected input data when

  

Source: Aboulhamid, El Mostapha - Département d'Informatique et recherche opérationnelle, Université de Montréal

 

Collections: Engineering