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Summary: 90272-1732/99/$10.00 © 1999 IEEE
Today's methodology for designing
state-of-the-art microprocessors involves mod-
eling at various levels of abstraction. In the
presynthesis phase, this can range from early-
stage, performance-only models to final-stage,
detailed register-transfer-level (RTL) models.
Hierarchical modeling requires the use of an
elaborate validation methodology to ensure
inter- and intralevel model integrity. The RTL
model, often coded in a hardware description
language (for example, Verilog or VHDL),
captures the logical behavior of the entire chip,
both in terms of function and cycle-by-cycle
pipeline flow timing. It is this model that is
subjected to simulation-based architectural
validation prior to actual tape-out of the
processor. The validated RTL specification
serves as the source reference model for syn-
thesizing the gate- and circuit-level processor
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