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SET-based nano-circuit simulation and design method using HSPICE Fengming Zhang, Rui Tang, Yong-Bin Kim*

Summary: SET-based nano-circuit simulation and design method using HSPICE
Fengming Zhang, Rui Tang, Yong-Bin Kim*
Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA
Received 13 August 2004; received in revised form 30 December 2004; accepted 24 January 2005
This paper presents a simulation and design method for complementary SET-based nano-circuits from a practical circuit design point of
view. HSPICE behavioral implementation of modified Lientschnig's SET model based on the orthodox theory and the Birth­Death Markov
chain is demonstrated and verified with Coulomb characteristics. It shows reduced CPU time, improvement of accuracy, and more
compatibility with other SPICE softwares on both Windows and Unix platforms. The proposed design methodology presents how to build
static CMOS-like SET circuits, and demonstrates that conventional CMOS circuit design methodologies are all applicable to SET circuit
designs based on the methodology. HSPICE simulation results show that, for 1 MU junction resistance, the power consumption of a SET
NAND2 gate is less than 0.3 pW, and the propagation delay for a SET XOR2 gate is 29.8 ns while driving a 10 aF load.
q 2005 Published by Elsevier Ltd.
PACS: 07.05.Tp; 85.35.Gv; 84.30.Kr; 73.23.Hk
1991 MSC: 00-Axx
Keywords: SET modeling; SET simulation with HSPICE; SET circuit design
1. Introduction
Traditional CMOS technology has dominated for several
decades. However, as silicon devices go into sub-100 nm
regime, defined by the National Science Foundation as


Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University


Collections: Engineering