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International Journal of Parallel Programming , Vol . 27, No. 5, 1999 Memory Renaming: Fast, Early and
 

Summary: International Journal of Parallel Programming , Vol . 27, No. 5, 1999
Memory Renaming: Fast, Early and
Accurate Processing of Memory
Communication
Gary S. Tyson1
and Todd M. Austin1
Received April 6, 1999; revised May 18, 1999
As processors continue to exploit more instruction level parallelism, greater
demands are placed on the performance of the memory system. In this paper,
we introduce a novel modification of the processor pipeline called memory
renaming. Memory renaming applies register access techniques to load and store
instructions to speed the processing of memory traffic. The approach works by
accurately predicting memory communication early in the pipeline and then
re-mapping the communication to fast physical registers. This work extends pre-
vious studies of data value and dependence speculation. When memory renam-
ing is added to the processor pipeline, renaming can be applied to 30 50% of
all memory references, translating to an overall improvement in execution time
of up to 14% for current pipeline configurations. As store forward delay times
grow larger, renaming support can lead to performance improvements of as
much as 42 %. Furthermore, this improvement is seen across all memory

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan

 

Collections: Engineering; Computer Technologies and Information Sciences