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A Novel Clocking Strategy for Dynamic Circuits Young Jun Lee, Jong-Jin Lim, Yong-Bin Kim
 

Summary: A Novel Clocking Strategy for Dynamic Circuits
Young Jun Lee, Jong-Jin Lim, Yong-Bin Kim
Northeastern University
ECE Department
360 Huntington Ave, Boston, USA
yjlee@ece.neu.edu, jlim@ece.neu.edu, ybk@ece.neu.edu
Abstract
This paper proposes a new clocking strategy for dynamic
circuit. It provides faster performance and smaller area
than conventional clocking scheme. The proposed clock-
ing scheme for dynamic circuits provides the solution of the
problem caused by logic polarity and clock skew problem si-
multaneously. To demonstrate the proposed clocking strat-
egy, a 32 bit Carry Look Ahead adder (CLA) is designed and
simulated using 0.25um CMOS technology to demonstrate
32.7± faster speed than the conventional clocking scheme
and 19.4±transistor counter reduction.
1. Introduction
Domino logic family has prevailed for high perfor-
mance CMOS applications because of its high speed ad-

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering