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Summary: PARALLELIZATION TECHNIQUES WITH
IMPROVED DEPENDENCE HANDLING
EASWARAN RAMAN
A DISSERTATION
PRESENTED TO THE FACULTY
OF PRINCETON UNIVERSITY
IN CANDIDACY FOR THE DEGREE
OF DOCTOR OF PHILOSOPHY
RECOMMENDED FOR ACCEPTANCE
BY THE DEPARTMENT OF
COMPUTER SCIENCE
ADVISOR: DAVID I. AUGUST
JUNE 2009
c Copyright by Easwaran Raman, 2009.
All Rights Reserved
Abstract
Continuing exponential growth in transistor density and diminishing returns from the in-
creasing transistor count have forced processor manufacturers to pack multiple processor
cores onto a single chip. These processors, known as multi-core processors, generally do
not improve the performance of single-threaded applications. Automatic parallelization has
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