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Appears in 19th Conference on Advanced Research in VLSI, Salt Lake City, UT, March 2001 Activity-Sensitive Flip-Flop and Latch Selection
 

Summary: Appears in 19th Conference on Advanced Research in VLSI, Salt Lake City, UT, March 2001
Activity-Sensitive Flip-Flop and Latch Selection
for Reduced Energy
Seongmoo Heo, Ronny Krashinsky, and Krste Asanovi┤c
MIT Laboratory for Computer Science, Cambridge, MA 02139
fheomoo,ronny,krsteg@mit.edu
Abstract
This work presents new techniques to evaluate the energy and delay of flip-flop and latch
designs and shows that no single existing design performs well across the wide range of
operating regimes present in complex systems. We propose the use of a selection of flip-
flop and latch designs, each tuned for different activation patterns and speed requirements.
We illustrate the use of our technique on a pipelined MIPS processor datapath running
SPECint95 benchmarks, where we reduce total flip-flop and latch energy by over 60%
without increasing cycle time.
1. Introduction
Flip-flops and latches (collectively referred to as timing elements in this paper) are crit-
ical components in modern synchronous VLSI designs. Timing element (TE) design has a
large impact on both system cycle time and system energy consumption and consequently
there has been significant interest in the development of fast and energy-efficient TE cir-
cuits [2, 10, 11, 12, 14, 15, 16, 17, 18]. The evaluation methodology presented in previous

  

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
AsanoviŠ, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

 

Collections: Computer Technologies and Information Sciences