Summary: This article was processed using the L a T E X macro package with LLNCS style
The construction of R, the process encapsulating the timing information, is
not as efficient as it could be. Any method for making timing verification more
efficient, such as partial order reductions, could in principle be incorporated into
our current scheme.
We believe that our work will be useful in applications such as asynchronous
circuits and hardware software codesign, where abstract descriptions of systems
necessarily include timing information.
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