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In Proceedings of the 32nd Annual International Symposium on Microarchitecture (MICRO-32), November 1999. Fetch Directed Instruction Prefetching
 

Summary: In Proceedings of the 32nd Annual International Symposium on Microarchitecture (MICRO-32), November 1999.
Fetch Directed Instruction Prefetching
Glenn Reinmany
Brad Caldery
Todd Austinz
y
Department of Computer Science and Engineering, University of California, San Diego
z
Electrical Engineering and Computer Science Department, University of Michigan
Abstract
Instruction supply is a crucial component of processor
performance. Instruction prefetching has been proposed as
a mechanism to help reduce instruction cache misses, which
in turn can help increase instruction supply to the processor.
In this paper we examine a new instruction prefetch ar-
chitecture called Fetch Directed Prefetching, and compare
it to the performance of next-line prefetching and streaming
buffers. This architecture uses a decoupled branch predic-
tor and instruction cache, so the branch predictor can run
ahead of the instruction cache fetch. In addition, we ex-

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan
Calder, Bradley - Department of Computer Science and Engineering, University of California at San Diego
Sair, Suleyman - Department of Electrical and Computer Engineering, North Carolina State University

 

Collections: Computer Technologies and Information Sciences; Engineering