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Evaluating Dynamic Core Coupling in a Scalable Tiled-CMP Architecture Daniel Sanchez, Juan L. Aragon and Jose M. Garcia

Summary: Evaluating Dynamic Core Coupling in a Scalable Tiled-CMP Architecture
Daniel S´anchez, Juan L. Arag´on and Jos´e M. Garc´ia
Departamento de Ingenier´ia y Tecnolog´ia de Computadores
Universidad de Murcia, Spain
Email: {dsanchez, jlaragon, jmgarcia}@ditec.um.es
To obtain benefit of the increasing transistor count
in current processors, designs are leading to CMPs
that will integrate tens or hundreds of processor cores
on-chip. However, scaling and voltage factors are
increasing susceptibility of architectures to transient,
intermittent and permanent faults, as well as process
A very recent solution found in literature consists
of Dynamic Core Coupling (DCC) [6]. DCC provides
a fault tolerant framework based on dynamic binding
of cores for re-execution. This technique relies on the
use of a shared-bus. However, for current and future
CMP architectures, more efficient designs are tiled-
CMPs, which are organized around a direct network,


Source: Aragón Alcaraz, Juan Luis - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia


Collections: Computer Technologies and Information Sciences