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Summary: Architectural Semantics for Practical Transactional Memory
Austen McDonald, JaeWoong Chung, Brian D. Carlstrom, Chi Cao Minh, Hassan Chafi,
Christos Kozyrakis and Kunle Olukotun
Computer Systems Laboratory
Stanford University
{austenmc, jwchung, bdc, caominh, hchafi, kozyraki, kunle}@stanford.edu
Abstract
Transactional Memory (TM) simplifies parallel program-
ming by allowing for parallel execution of atomic tasks.
Thus far, TM systems have focused on implementing trans-
actional state buffering and conflict resolution. Missing is a
robust hardware/software interface, not limited to simplis-
tic instructions defining transaction boundaries. Without
rich semantics, current TM systems cannot support basic
features of modern programming languages and operating
systems such as transparent library calls, conditional syn-
chronization, system calls, I/O, and runtime exceptions.
This paper presents a comprehensive instruction set ar-
chitecture (ISA) for TM systems. Our proposal introduces
three key mechanisms: two-phase commit; support for soft-
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