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Ecient Sorting Using Registers and Caches Rajiv Wickremesinghe, Lars Arge, Je rey S. Chase, Je rey Scott Vitter
 

Summary: E∆cient Sorting Using Registers and Caches
Rajiv Wickremesinghe, Lars Arge, Je rey S. Chase, Je rey Scott Vitter
Duke University, Durham, NC, U.S.A.
Modern computer systems have increasingly complex memory systems. Common machine models
for algorithm analysis do not re ect many of the features of these systems, e.g., large register sets,
lockup-free caches, cache hierarchies, associativity, cache line fetching, and streaming behavior.
Inadequate models lead to poor algorithmic choices and an incomplete understanding of algorithm
behavior on real machines.
A key step toward developing better models is to quantify the performance e ects of features
not re ected in the models. This paper explores the e ect of memory system features on sorting
performance. We introduce a new cache-conscious sorting algorithm, R-merge, which achieves
better performance in practice over algorithms that are superior in the theoretical models. R-
merge is designed to minimize memory stall cycles rather than cache misses by considering features
common to many system designs.
1. INTRODUCTION
Program performance on today's computer systems is largely determined by in-
teractions with the memory system. While new compiler techniques can help to
improve a program's memory system behavior, algorithmic choices play a key role in
determining memory access patterns for data-intensive computation. Despite recent
progress, development of software that can perform well on on modern machines

  

Source: Arge, Lars - Department of Computer Science, Aarhus Universitet

 

Collections: Computer Technologies and Information Sciences