Summary: 1. This research was supported by General Motors R&D Center.
Digest of Papers: IEEE International On-Line Testing Workshop, 1996, pp. 164-167.
This paper briefly reviews on-line built-in self-test
(BIST) and shows its importance in concurrent checking.
Then a new approach for the design of deterministic BIST
hardware test generators is presented. The approach uses
high-level models of circuits to identify the classes of tests
needed for complete coverage of faults. The test generator
is then designed with the following goals: scalability, near-
minimal error latency, and complete coverage of the mod-
eled faults. Moreover, the test generators produced are sim-
ple and have low hardware overhead. Preliminary case
studies of carry-lookahead adders, arithmetic logic units,
and barrel shifters show the usefulness of this technique.
There are four primary parameters to be considered in
the design of any on-line testing scheme:
· Error coverage (EC): This is defined as the percentage
of modeled errors that are detected, for example, all