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Extending the Scalability of Single Chip Stream Processors with On-chip Caches Ali Bakhoda and Tor M. Aamodt
 

Summary: Extending the Scalability of Single Chip Stream Processors with On-chip Caches
Ali Bakhoda and Tor M. Aamodt
University of British Columbia,
Vancouver, BC, Canada
{bakhoda,aamodt}@ece.ubc.ca
Abstract
As semiconductor scaling continues, more transistors
can be put onto the same chip despite growing challenges
in clock frequency scaling. Stream processor architectures
can make effective use of these additional resources for ap-
propriate applications. However, it is important that pro-
grammer effort be amortized across future generations of
stream processor architectures. Current industry projec-
tions suggest a single chip may be able to integrate several
thousand 64-bit floating-point ALUs within the next decade.
Future designs will require significantly larger, scalable on-
chip interconnection networks, which will likely increase
memory access latency. While the capacity of the explicitly
managed local store of current stream processor architec-
tures could be enlarged to tolerate the added latency, exist-

  

Source: Aamodt, Tor - Department of Electrical and Computer Engineering, University of British Columbia

 

Collections: Engineering; Computer Technologies and Information Sciences