Class network routing
Abstract
Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast. Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.
- Inventors:
-
- Princeton, NJ
- Ridgefield, CT
- Croton On Hudson, NY
- Yorktown Heights, NY
- Mount Kisco, NY
- Irvington, NY
- Cortlandt Manor, NY
- Bedford Hills, NY
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 988822
- Patent Number(s):
- 7587516
- Application Number:
- 10/468,999
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
F - MECHANICAL ENGINEERING F04 - POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS F04D - NON-POSITIVE-DISPLACEMENT PUMPS
F - MECHANICAL ENGINEERING F24 - HEATING F24F - AIR-CONDITIONING
- DOE Contract Number:
- W-7405-ENG-48
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Bhanot, Gyan, Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Philip, Steinmacher-Burow, Burkhard D, Takken, Todd E, and Vranas, Pavlos M. Class network routing. United States: N. p., 2009.
Web.
Bhanot, Gyan, Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Philip, Steinmacher-Burow, Burkhard D, Takken, Todd E, & Vranas, Pavlos M. Class network routing. United States.
Bhanot, Gyan, Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Philip, Steinmacher-Burow, Burkhard D, Takken, Todd E, and Vranas, Pavlos M. Tue .
"Class network routing". United States. https://www.osti.gov/servlets/purl/988822.
@article{osti_988822,
title = {Class network routing},
author = {Bhanot, Gyan and Blumrich, Matthias A and Chen, Dong and Coteus, Paul W and Gara, Alan G and Giampapa, Mark E and Heidelberger, Philip and Steinmacher-Burow, Burkhard D and Takken, Todd E and Vranas, Pavlos M},
abstractNote = {Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast. Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Sep 08 00:00:00 EDT 2009},
month = {Tue Sep 08 00:00:00 EDT 2009}
}
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conference, January 1988
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A systolic architecture for fast dense matrix inversion
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An optimal scheduling procedure for matrix inversion on linear array at a processor level
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