Apparatus and method for defect testing of integrated circuits

Soden, Jerry M

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Title: Apparatus and method for defect testing of integrated circuits

Abstract

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

Inventors:

Cole, Jr., Edward I. ^[1]; Soden, Jerry M ^[2]

(Albuquerque, NM)
Placitas, NM

Issue Date:: Sat Jan 01 00:00:00 EST 2000

Research Org.:: Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)

OSTI Identifier:: 872882

Patent Number(s):: 6031386

Assignee:: Sandia Corporation (Albuquerque, NM)

Patent Classifications (CPCs):: G - PHYSICS G01 - MEASURING G01R - MEASURING ELECTRIC VARIABLES

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G - PHYSICS G01 - MEASURING G01R - MEASURING ELECTRIC VARIABLES
G01R31/3004 - {Current or voltage test}

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DOE Contract Number:: AC04-94AL85000

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: apparatus; method; defect; testing; integrated; circuits; failure-mechanism; ics; disclosed; provides; operating; voltage; dd; measures; transient; component; ddt; signal; produced; response; switching; transients; occur; vectors; provided; inputs; amplitude; time; delay; distinguish; defective; defect-free; measured; digitizer; digital; oscilloscope; tester; input; applications; process; manufacture; qualifying; reliability; operating voltage; apparatus provides; time delay; integrated circuits; integrated circuit; transient digitizer; transient voltage; /324/

Citation Formats


                    Cole, Jr., Edward I., and Soden, Jerry M. Apparatus and method for defect testing of integrated circuits.  United States: N. p., 2000. 
        Web.

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                    Cole, Jr., Edward I., & Soden, Jerry M. Apparatus and method for defect testing of integrated circuits.  United States.

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                    Cole, Jr., Edward I., and Soden, Jerry M. Sat .  
        "Apparatus and method for defect testing of integrated circuits".  United States.  https://www.osti.gov/servlets/purl/872882.

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@article{osti_872882,

  title        = {Apparatus and method for defect testing of integrated circuits},

  author       = {Cole, Jr., Edward I. and Soden, Jerry M},

  abstractNote = {An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Sat Jan 01 00:00:00 EST 2000},

  month        = {Sat Jan 01 00:00:00 EST 2000}

}

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Works referenced in this record:

On the effect of I/sub SSQ/ testing in reducing early failure rate
conference, January 1995

Wallquist, K. M.
Proceedings of 1995 IEEE International Test Conference (ITC)
https://doi.org/10.1109/TEST.1995.529924

IC failure analysis: techniques and tools for quality reliability improvement
journal, May 1993

Soden, J. M.; Anderson, R. E.
Proceedings of the IEEE, Vol. 81, Issue 5
https://doi.org/10.1109/5.220902

I/sub DD/ pulse response testing on analog and digital CMOS circuits
conference, January 1993

Beasley, J. S.; Ramamurthy, H.; Ramirez-Angulo, J.
Proceedings of IEEE International Test Conference - (ITC)
https://doi.org/10.1109/TEST.1993.470641

High resolution I/sub DDQ/ characterization and testing-practical issues
conference, January 1996

Righter, A. W.; Soden, J. M.; Beegle, R. W.
Proceedings International Test Conference 1996. Test and Design Validity
https://doi.org/10.1109/TEST.1996.556970

Digital integrated circuit testing using transient signal analysis
conference, January 1996

Plusquellic, J. F.; Chiarulli, D. M.; Levitan, S. P.
Proceedings International Test Conference 1996. Test and Design Validity
https://doi.org/10.1109/TEST.1996.557062

A general purpose I/sub DDQ/ measurement circuit
conference, January 1993

Wallquist, K.; Righter, A. W.; Hawkins, C. F.
Proceedings of IEEE International Test Conference - (ITC)
https://doi.org/10.1109/TEST.1993.470639

I DDQ testing: A review
journal, December 1992

Soden, Jerry M.; Hawkins, Charles F.; Gulati, Ravi K.
Journal of Electronic Testing, Vol. 3, Issue 4
https://doi.org/10.1007/BF00135333

Iddq test: sensitivity analysis of scaling
conference, January 1996

Williams, T. W.; Dennard, R. H.; Kapur, R.
Proceedings International Test Conference 1996. Test and Design Validity
https://doi.org/10.1109/TEST.1996.557138

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Similar Records

Title: Apparatus and method for defect testing of integrated circuits

Abstract

Citation Formats

On the effect of I/sub SSQ/ testing in reducing early failure rate conference, January 1995

IC failure analysis: techniques and tools for quality reliability improvement journal, May 1993

I/sub DD/ pulse response testing on analog and digital CMOS circuits conference, January 1993

High resolution I/sub DDQ/ characterization and testing-practical issues conference, January 1996

Digital integrated circuit testing using transient signal analysis conference, January 1996

A general purpose I/sub DDQ/ measurement circuit conference, January 1993

I DDQ testing: A review journal, December 1992

Iddq test: sensitivity analysis of scaling conference, January 1996

On the effect of I/sub SSQ/ testing in reducing early failure rate
conference, January 1995

IC failure analysis: techniques and tools for quality reliability improvement
journal, May 1993

I/sub DD/ pulse response testing on analog and digital CMOS circuits
conference, January 1993

High resolution I/sub DDQ/ characterization and testing-practical issues
conference, January 1996

Digital integrated circuit testing using transient signal analysis
conference, January 1996

A general purpose I/sub DDQ/ measurement circuit
conference, January 1993

I DDQ testing: A review
journal, December 1992

Iddq test: sensitivity analysis of scaling
conference, January 1996