Data flow machine for data driven computing
Abstract
A data flow computer which of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status but to indicate whether the stored information in the corresponding datamore »
- Inventors:
-
- Albuquerque, NM
- Issue Date:
- Research Org.:
- Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
- OSTI Identifier:
- 870150
- Patent Number(s):
- 5465368
- Assignee:
- United States of America as represented by United States (Washington, DC)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC04-76DP00789
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- data; flow; machine; driven; computing; computer; disclosed; utilizes; processor; node; architecture; apparatus; preferred; embodiment; plurality; first-in-first-out; fifo; registers; related; memories; makes; calculations; control; unit; generate; signals; enable; appropriate; register; receiving; result; particular; input; receive; information; form; outside; source; provide; output; recipient; internal; comprised; commonly; addressed; parameter; memory; holds; parameters; opcode; instruction; target; address; tag; contains; status; bits; bit; indicates; corresponding; indicate; stored; reused; outputs; fire; signal; valid; fired; tag memory; parameter memory; fifo registers; data driven; provide output; flow memories; particular embodiment; processor node; preferred embodiment; control unit; data flow; fifo register; memory holds; provide information; register receiving; related data; memory outputs; node architecture; status bits; bit indicates; appropriate fifo; addressed memories; processor makes; output fifo; output information; opcode memory; outside source; target memory; output address; outside recipient; commonly addressed; receive input; status bit; stored information; memory contains; flow computer; generate signals; corresponding data; input information; driven computing; driven processor; corresponding parameter; contains status; data parameter; internal fifo; input fifo; information form; flow machine; /712/
Citation Formats
Davidson, George S, and Grafe, Victor G. Data flow machine for data driven computing. United States: N. p., 1995.
Web.
Davidson, George S, & Grafe, Victor G. Data flow machine for data driven computing. United States.
Davidson, George S, and Grafe, Victor G. Sun .
"Data flow machine for data driven computing". United States. https://www.osti.gov/servlets/purl/870150.
@article{osti_870150,
title = {Data flow machine for data driven computing},
author = {Davidson, George S and Grafe, Victor G},
abstractNote = {A data flow computer which of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status but to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a "fire" signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Sun Jan 01 00:00:00 EST 1995},
month = {Sun Jan 01 00:00:00 EST 1995}
}