DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Fault-tolerant corrector/detector chip for high-speed data processing

Abstract

An internally fault-tolerant data error detection and correction integrated circuit device (10) and a method of operating same. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum is provided with a relatively short eight bits of data-protecting parity. The 32-bits of data by eight bits of parity is partitioned into eight 4-bit nibbles and two 4-bit nibbles, respectively. For data flowing towards the processor the data and parity nibbles are checked in parallel and in a single operation employing a dual orthogonal basis technique. The dual orthogonal basis increase the efficiency of the implementation. Any one of ten (eight data, two parity) nibbles are correctable if erroneous, or two different erroneous nibbles are detectable. For data flowing away from the processor the appropriate parity nibble values are calculated and transmitted to the system along with the data. The device regenerates parity values for data flowing in either direction and compares regenerated to generated parity with a totally self-checking equality checker. As such, the device is self-validating and enabled to both detect and indicate an occurrence of an internal failure. A generalization of themore » device to protect 64-bit data with 16-bit parity to protect against byte-wide errors is also presented.

Inventors:
 [1];  [2];  [3];  [4]
  1. San Ramon, CA
  2. (Danville, CA)
  3. Davis, CA
  4. Fayetteville, NY
Issue Date:
Research Org.:
AT&T
OSTI Identifier:
869174
Patent Number(s):
5291496
Assignee:
United States of America as represented by United States (Washington, DC)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
DOE Contract Number:  
AC04-76DP00789
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
fault-tolerant; corrector; detector; chip; high-speed; data; processing; internally; error; detection; correction; integrated; circuit; device; 10; method; operating; functions; bidirectional; buffer; 32-bit; processor; remainder; provides; datum; provided; relatively; eight; bits; data-protecting; parity; 32-bits; partitioned; 4-bit; nibbles; respectively; flowing; towards; checked; parallel; single; operation; employing; dual; orthogonal; basis; technique; increase; efficiency; implementation; correctable; erroneous; detectable; appropriate; nibble; values; calculated; transmitted; regenerates; direction; compares; regenerated; generated; totally; self-checking; equality; checker; self-validating; enabled; detect; indicate; occurrence; internal; failure; generalization; protect; 64-bit; 16-bit; byte-wide; errors; bit data; data processing; integrated circuit; data flow; speed data; circuit device; single operation; operation employing; data processor; error detection; high-speed data; bidirectional data; /714/

Citation Formats

Andaleon, David D, Napolitano, Jr., Leonard M., Redinbo, G Robert, and Shreeve, William O. Fault-tolerant corrector/detector chip for high-speed data processing. United States: N. p., 1994. Web.
Andaleon, David D, Napolitano, Jr., Leonard M., Redinbo, G Robert, & Shreeve, William O. Fault-tolerant corrector/detector chip for high-speed data processing. United States.
Andaleon, David D, Napolitano, Jr., Leonard M., Redinbo, G Robert, and Shreeve, William O. Sat . "Fault-tolerant corrector/detector chip for high-speed data processing". United States. https://www.osti.gov/servlets/purl/869174.
@article{osti_869174,
title = {Fault-tolerant corrector/detector chip for high-speed data processing},
author = {Andaleon, David D and Napolitano, Jr., Leonard M. and Redinbo, G Robert and Shreeve, William O},
abstractNote = {An internally fault-tolerant data error detection and correction integrated circuit device (10) and a method of operating same. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum is provided with a relatively short eight bits of data-protecting parity. The 32-bits of data by eight bits of parity is partitioned into eight 4-bit nibbles and two 4-bit nibbles, respectively. For data flowing towards the processor the data and parity nibbles are checked in parallel and in a single operation employing a dual orthogonal basis technique. The dual orthogonal basis increase the efficiency of the implementation. Any one of ten (eight data, two parity) nibbles are correctable if erroneous, or two different erroneous nibbles are detectable. For data flowing away from the processor the appropriate parity nibble values are calculated and transmitted to the system along with the data. The device regenerates parity values for data flowing in either direction and compares regenerated to generated parity with a totally self-checking equality checker. As such, the device is self-validating and enabled to both detect and indicate an occurrence of an internal failure. A generalization of the device to protect 64-bit data with 16-bit parity to protect against byte-wide errors is also presented.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Sat Jan 01 00:00:00 EST 1994},
month = {Sat Jan 01 00:00:00 EST 1994}
}

Works referenced in this record:

Bit-serial Reed - Solomon encoders
journal, November 1982


On t-error correcting/all unidirectional error detecting codes
journal, January 1989


An efficient class of unidirectional error detecting/correcting codes
journal, July 1988


Fault-Tolerant Decoders for Cyclic Error-Correcting Codes
journal, January 1987


An architecture for electrically configurable gate arrays
journal, April 1989


Fast Burst Error-Correction Scheme with Fire Code
journal, July 1984


A General Class of Maximal Codes ror Computer Applications
journal, December 1972


A 10 MHz (255, 223) Reed-Solomon decoder
conference, January 1988


Finite Fields for Computer Scientists and Engineers
book, January 1987


Unidirectional byte error detecting codes for computer memory systems
journal, April 1990


Unidirectional 9-bit byte error detecting codes for computer memory systems
conference, January 1989


b-Adjacent Error Correction
journal, July 1970