FPGA-based computing system for processing data in size, weight, and power constrained environments
Abstract
Technologies that are well-suited for use in size, weight, and power (SWAP)-constrained environments are described herein. A host controller dispatches data processing instructions to hardware acceleration engines (HAEs) of one or more field programmable gate arrays (FPGAs) and further dispatches data transfer instructions to a memory controller, such that the HAEs perform processing operations on data stored in local memory devices of the HAEs in parallel with other data being transferred from external memory devices coupled to the FPGA(s) to the local memory devices.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org.:
- USDOE National Nuclear Security Administration (NNSA)
- OSTI Identifier:
- 1892875
- Patent Number(s):
- 11314508
- Application Number:
- 17/163,754
- Assignee:
- National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
- DOE Contract Number:
- NA0003525
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 02/01/2021
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Napier, Matthew, Lee, David S., and Anders, Gregory Philip. FPGA-based computing system for processing data in size, weight, and power constrained environments. United States: N. p., 2022.
Web.
Napier, Matthew, Lee, David S., & Anders, Gregory Philip. FPGA-based computing system for processing data in size, weight, and power constrained environments. United States.
Napier, Matthew, Lee, David S., and Anders, Gregory Philip. Tue .
"FPGA-based computing system for processing data in size, weight, and power constrained environments". United States. https://www.osti.gov/servlets/purl/1892875.
@article{osti_1892875,
title = {FPGA-based computing system for processing data in size, weight, and power constrained environments},
author = {Napier, Matthew and Lee, David S. and Anders, Gregory Philip},
abstractNote = {Technologies that are well-suited for use in size, weight, and power (SWAP)-constrained environments are described herein. A host controller dispatches data processing instructions to hardware acceleration engines (HAEs) of one or more field programmable gate arrays (FPGAs) and further dispatches data transfer instructions to a memory controller, such that the HAEs perform processing operations on data stored in local memory devices of the HAEs in parallel with other data being transferred from external memory devices coupled to the FPGA(s) to the local memory devices.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Apr 26 00:00:00 EDT 2022},
month = {Tue Apr 26 00:00:00 EDT 2022}
}
Works referenced in this record:
Flexible Neural Network Accelerator and Methods Therefor
patent-application, May 2018
- Deisher, Michael E.; Falik, Ohad
- US Patent Application 15/343,036; 2018/0121796 Al
Synchronization of parallel memory accesses in a dataflow circuit
patent, June 2013
- Bennett, David W.; Sundararajan, Prasanna
- US Patent Document 8,473,880
Memory-based distributed processor architecture
patent, June 2021
- Sity, Elad; Hillel, Eliad
- US Patent Document 11,023,336
Logic multiprocessor for FPGA implementation
patent, August 2007
- Butts, Michael
- US Patent Document 7,260,794
Deep neural network processing on hardware accelerators with stacked memory
patent, January 2020
- Burger, Douglas C.; Chiou, Derek; Chung, Eric S.
- US Patent Document 10,540,588
Method and apparatus for transferring data between two different interfaces
patent, August 2012
- Wennekamp, Wayne E.; Elkins, Adam; Shimanek, Schuyler E.
- US Patent Document 8,239,590
Hierarchical General Register File (GRF) for Execution Block
patent-application, October 2018
- Appu, Abhishek R.; Koker, Altung; Ray, Joydeep
- US Patent Application 15/477,033; 2018/0285106 Al
Common shared memory in a verification system
patent, November 2015
- Tseng, Ping-Sheng; Lin, Sharon Sheau-Pyng; Shen, Quincy Kun-Hsu
- US Patent Document 9,195,784
Parallelism in Serial Pipeline Processing
patent-application, October 2021
- Herbert, Tom
- US Patent Application 17/233,149; 2021/0326175 Al
Storage system having an in-line hardware accelerator
patent, March 2021
- Ben-Yehuda, Shmuel; Efrati, Ofir; Grimberg, Sagi
- US Patent Document 10,956,346