Structured wafer for device processing
Abstract
A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1164347
- Patent Number(s):
- 8895364
- Application Number:
- 14/243,665
- Assignee:
- Sandia Corporation (Albuquerque, NM)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- AC04-94AL85000
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 36 MATERIALS SCIENCE; 42 ENGINEERING
Citation Formats
Okandan, Murat, and Nielson, Gregory N. Structured wafer for device processing. United States: N. p., 2014.
Web.
Okandan, Murat, & Nielson, Gregory N. Structured wafer for device processing. United States.
Okandan, Murat, and Nielson, Gregory N. Tue .
"Structured wafer for device processing". United States. https://www.osti.gov/servlets/purl/1164347.
@article{osti_1164347,
title = {Structured wafer for device processing},
author = {Okandan, Murat and Nielson, Gregory N},
abstractNote = {A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Nov 25 00:00:00 EST 2014},
month = {Tue Nov 25 00:00:00 EST 2014}
}
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Works referencing / citing this record:
Fast process flow, on-wafer interconnection and singulation for MEPV
patent, August 2017
- Okandan, Murat; Nielson, Gregory N.; Cruz-Campa, Jose Luis
- US Patent Document 9,748,415
Fast process flow, on-wafer interconnection and singulation for MEPV
patent, January 2017
- Okandan, Murat; Nielson, Gregory N.; Cruz-Campa, Jose Luis
- US Patent Document 9,559,219