Method and apparatus for low power analog-to-digital conversion
Abstract
A method and apparatus for analog-to-digital conversion. An Analog-to-Digital Converter (ADC) includes M ADC.sub.j, j=1, 2, . . . , M. Each ADC.sub.j comprises a number of cells each of which comprises a first switch, a second switch, a current sink and an inverter. An inverter of a cell in an ADC.sub.j changes state in response to a current associate with an input signal of the ADC.sub.j exceeding a threshold, thus switching on the next cell. Each ADC.sub.j is enabled to perform analog-to-digital conversion on a residual current of a previous ADC.sub.j-1 after the previous ADC.sub.j-1 has completed its analog-to-digital conversion and has been disabled.
- Inventors:
- Issue Date:
- Research Org.:
- Brookhaven National Laboratory (BNL), Upton, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1107572
- Patent Number(s):
- 8547271
- Application Number:
- 13/474,060
- Assignee:
- Brookhaven Science Associates, LLC (Upton, NY)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
- DOE Contract Number:
- AC02-98CH10886
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING
Citation Formats
De Geronimo, Gianluigi, and Nambiar, Neena. Method and apparatus for low power analog-to-digital conversion. United States: N. p., 2013.
Web.
De Geronimo, Gianluigi, & Nambiar, Neena. Method and apparatus for low power analog-to-digital conversion. United States.
De Geronimo, Gianluigi, and Nambiar, Neena. Tue .
"Method and apparatus for low power analog-to-digital conversion". United States. https://www.osti.gov/servlets/purl/1107572.
@article{osti_1107572,
title = {Method and apparatus for low power analog-to-digital conversion},
author = {De Geronimo, Gianluigi and Nambiar, Neena},
abstractNote = {A method and apparatus for analog-to-digital conversion. An Analog-to-Digital Converter (ADC) includes M ADC.sub.j, j=1, 2, . . . , M. Each ADC.sub.j comprises a number of cells each of which comprises a first switch, a second switch, a current sink and an inverter. An inverter of a cell in an ADC.sub.j changes state in response to a current associate with an input signal of the ADC.sub.j exceeding a threshold, thus switching on the next cell. Each ADC.sub.j is enabled to perform analog-to-digital conversion on a residual current of a previous ADC.sub.j-1 after the previous ADC.sub.j-1 has completed its analog-to-digital conversion and has been disabled.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Oct 01 00:00:00 EDT 2013},
month = {Tue Oct 01 00:00:00 EDT 2013}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.
Works referenced in this record:
Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC
conference, May 2008
- Esperanca, B.; Goes, J.; Tavares, R.
- 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008
An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 $\mu$m CMOS
journal, February 2010
- Peach, Charles T.; Moon, Un-Ku; Allstot, David J.
- IEEE Journal of Solid-State Circuits, Vol. 45, Issue 2
A 10 MS/s 11-bit 0.19 mm$^{2}$ Algorithmic ADC With Improved Clocking Scheme
journal, September 2009
- Kim, Min Gyu; Hanumolu, Pavan Kumar; Moon, Un-Ku
- IEEE Journal of Solid-State Circuits, Vol. 44, Issue 9
A low power 12-bit and 25-MS/s pipelined ADC for the ILC / ECAL integrated readout
conference, October 2008
- Rarbi, Fatah; Dzahini, Daniel; Gallin-Martel, Laurent
- 2008 IEEE Nuclear Science Symposium and Medical Imaging conference (2008 NSS/MIC), 2008 IEEE Nuclear Science Symposium Conference Record
Current amplifier and current mode analog/digital converter using the same
patent, October 1999
- Yasuda, Akira
- US Patent Document 5,963,158
Method and apparatus for current-mode ADC
patent, May 2010
- Poon, Chi-Sang; Rachmuth, Guy
- US Patent Document 7,714,762
Sample and hold circuit and active pixel sensor array sampling system utilizing same
patent, June 2008
- Beck, Jeffery; Borg, Matthew M.
- US Patent Document 7,388,608
A cost-efficient high-speed 12-bit pipeline ADC in 0.18-/spl mu/m digital CMOS
journal, July 2005
- Andersen, T. N.; Hernes, B.; Briskemyr, A.
- IEEE Journal of Solid-State Circuits, Vol. 40, Issue 7
A 12-bit fully differential 2MS/s successive approximation analog-to-digital converter with reduced power consumption
conference, April 2010
- Davidovic, M.; Zach, G.; Zimmermann, H.
- 2010 IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Analog-to-digital converter survey and analysis
journal, April 1999
- Walden, R. H.
- IEEE Journal on Selected Areas in Communications, Vol. 17, Issue 4
A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC
journal, November 2010
- Chung, Yung-Hui; Wu, Jieh-Tsorng
- IEEE Journal of Solid-State Circuits
A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC
journal, December 2009
- Brooks, Lane; Lee, Hae-Seung
- IEEE Journal of Solid-State Circuits, Vol. 44, Issue 12
Method and apparatus for clockless analog-to-digital conversion and peak detection
patent, March 2007
- DeGeronimo, Gianluigi
- US Patent Document 7,187,316
A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC
journal, October 2009
- Lee, Jongwoo; Kang, Joshua; Park, Sunghyun
- IEEE Journal of Solid-State Circuits, Vol. 44, Issue 10
A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s
journal, May 2010
- van Elzakker, Michiel; van Tuijl, Ed; Geraedts, Paul
- IEEE Journal of Solid-State Circuits, Vol. 45, Issue 5
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
journal, April 2010
- Liu, Chun-Cheng; Chang, Soon-Jyh; Huang, Guan-Ying
- IEEE Journal of Solid-State Circuits, Vol. 45, Issue 4