Title: Methods for fabrication of positional and compositionally controlled nanostructures on substrate

Abstract

Fabrication methods disclosed herein provide for a nanoscale structure or a pattern comprising a plurality of nanostructures of specific predetermined position, shape and composition, including nanostructure arrays having large area at high throughput necessary for industrial production. The resultant nanostracture patterns are useful for nanostructure arrays, specifically sensor and catalytic arrays.

Inventors:

Zhu, Ji; Grunes, Jeff; Choi, Yang-Kyu; Bokor, Jeffrey; Somorjai, Gabor

Issue Date:

Tue Jul 16 00:00:00 EDT 2013

Research Org.:

Univ. of California, Oakland, CA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1087891

Patent Number(s):

8486287

Application Number:

10/599,106

Assignee:

The Regents of the University of California (Oakland, CA)

Patent Classifications (CPCs):

B - PERFORMING OPERATIONS B81 - MICROSTRUCTURAL TECHNOLOGY B81C - PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS

B - PERFORMING OPERATIONS B82 - NANOTECHNOLOGY B82Y - SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES

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B - PERFORMING OPERATIONS B81 - MICROSTRUCTURAL TECHNOLOGY B81C - PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS

B81C1/00111 - {Tips, pillars, i.e. raised structures

B - PERFORMING OPERATIONS B82 - NANOTECHNOLOGY B82Y - SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES

B82Y10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

G - PHYSICS G03 - PHOTOGRAPHY G03F - PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES

G03F7/40 - Treatment after imagewise removal, e.g. baking

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

H01L21/3086 - {characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment}
H01L21/3088 - {Process specially adapted to improve the resolution of the mask}
H01L29/0665 - {the shape of the body defining a nanostructure
H01L29/0673 - {oriented parallel to a substrate}
H01L29/0676 - {oriented perpendicular or at an angle to a substrate}
H01L29/66795 - {with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET}
H01L29/785 - {having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET}

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DOE Contract Number:  

AC03-76SF00098

Resource Type:

Patent

Country of Publication:

United States

Language:

English

Subject:

36 MATERIALS SCIENCE