SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture
- Keio Univ., Yokohama (Japan)
Simple Serial Synchronized (SSS) Multistage Interconnection Network (MIN) is a novel MIN architecture for connecting processors and memory modules in multiprocessors. Synchronized bit-serial communication simplifies the structure/control, and also solves the pin-limitation problem. Here, design, implementation, and evaluation of a multiprocessor prototype called SNAIL with the SSS-MIN are presented. The heart of SNAIL is the prototype 1 {mu} CMOS SSS-MIN gate array chip which exchanges packets from 16 inputs with 50MHz clock. The message combining is implemented only with 20% increases of the hardware. From the empirical evaluation with some application programs, it appears that the latency and synchronization overhead of the SSS-MIN are tolerable, and the bandwidth of the SSS-MIN is sufficient. Although the performance improvement with the bit serial message combine is not so large (1%) when instructions are stored in the local memory, it becomes up to 400% when instructions are stored in the shared memory.
- OSTI ID:
- 98891
- Report Number(s):
- CONF-940856-; TRN: 94:008346-0023
- Resource Relation:
- Conference: 1994 international conference on parallel processing, St. Charles, IL (United States), 15-19 Aug 1994; Other Information: PBD: 1994; Related Information: Is Part Of Proceedings of the 1994 international conference on parallel processing. Volume 1: Architecture; Agrawal, D.P. [ed.]; PB: 330 p.
- Country of Publication:
- United States
- Language:
- English
Similar Records
Nonuniform traffic spots (NUTS) in multistage interconnection networks
RT-cube: An interconnection network architecture for multiprocessor systems