Timing discriminator using leading-edge extrapolation

Patent · Sat Jan 01 00:00:00 EST 1983

OSTI ID:864810

Gottschalk, Bernard ^[1]

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1. Palo Alto, CA

A discriminator circuit to recover timing information from slow-rising pulses by means of an output trailing edge, a fixed time after the starting corner of the input pulse, which is nearly independent of risetime and threshold setting. This apparatus comprises means for comparing pulses with a threshold voltage; a capacitor to be charged at a certain rate when the input signal is one-third threshold voltage, and at a lower rate when the input signal is two-thirds threshold voltage; current-generating means for charging the capacitor; means for comparing voltage capacitor with a bias voltage; a flip-flop to be set when the input pulse reaches threshold voltage and reset when capacitor voltage reaches the bias voltage; and a clamping means for discharging the capacitor when the input signal returns below one-third threshold voltage.

• Research Organization: SLAC National Accelerator Laboratory (SLAC), Menlo Park, CA (United States)
• DOE Contract Number: AC03-76SF00515
• Assignee: United States of America as represented by United States (Washington, DC)
• Patent Number(s): US 4421995
• OSTI ID: 864810
• Country of Publication: United States
• Language: English

Related Subjects

timing
discriminator
leading-edge
extrapolation
circuit
recover
information
slow-rising
pulses
means
output
trailing
edge
fixed
time
starting
corner
input
pulse
nearly
independent
risetime
threshold
setting
apparatus
comprises
comparing
voltage
capacitor
charged
rate
signal
one-third
two-thirds
current-generating
charging
bias
flip-flop
set
reaches
reset
clamping
discharging
returns
below
threshold voltage
generating means
apparatus comprises
input signal
bias voltage
trailing edge
input pulse
comprises means
pulse reaches
apparatus comprise
nearly independent
timing information
voltage capacitor
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