Hardware-assisted replay of microprocessor programs

Book · Tue Jan 01 00:00:00 EST 1991

OSTI ID:7205533

Bacon, D F; Goldstein, S C

Shared-memory parallel programs can be highly non-deterministic due to the unpredictable order in which shared references are satisfied. However, deterministic execution is extremely important for debugging and can also be used for fault-tolerance and other replay-based algorithms. This paper presents a hardware/software design that allows the order of memory references in a parallel program to be logged efficiently by recording a subset of the cache traffic between memory and the CPU's. This log can then be used along with hardware and software control to replay execution. The authors simulate memory and cache traffic for several parallel programs to determine the costs and characteristics of our scheme for realistic applications. The authors then use the information from the simulation to analyze the potential performance under a number of different system parameters.

• OSTI ID: 7205533
• Resource Relation: Other Information: Technical Report CSD 91/624
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
COMPUTER CODES
PARALLEL PROCESSING
PERFORMANCE
COMPUTERIZED CONTROL SYSTEMS
COMPUTERIZED SIMULATION
FAULT TOLERANT COMPUTERS
MEMORY DEVICES
PARAMETRIC ANALYSIS
SYSTEMS ANALYSIS
COMPUTERS
CONTROL SYSTEMS
DIGITAL COMPUTERS
ON-LINE CONTROL SYSTEMS
ON-LINE SYSTEMS
PROGRAMMING
SIMULATION
990200* - Mathematics & Computers