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Title: 570-ps 13-m W Josephson 1-kbit NDRO RAM

Journal Article · · IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA)
; ; ; ; ;  [1]
  1. Microelectronics Research Labs., NEC Corp., Ibaraki (JP)

This paper reports Josephson 1-kbit random access memories (RAM's) fabricated using Nb multilayer planarization technology with Nb/AlO{sub {ital x}}/Nb junctions and Mo resistors. The RAM design has been reported previously. The RAM consists of a 32 {times} 32-bit nondestructive readout (NDRO) memory cell array and peripheral circuits. The NDRO memory cell consists of a loop storing three flux quanta and two 3-junction interferometer gates. The peripheral circuits consist of decoders with address inverters, drivers, a sense circuit, and reset circuits, where resistor-coupled Josephson logic (RCJL) circuits are used as basic circuits. The RAM circuit size is 4.4 {times} 4.4 mm{sup 2}, and the memory cell size is 65 {times} 65 {mu}m{sup 2}. About 10000 Nb/AlO{sub {ital x}}/Nb junctions with 1030-A/cm{sup 2} critical current density were contained in the RAM. Minimum line and space widths were 3 and 2 {mu}m, respectively. The Mo resistors had 1.2 {approximately} 1.3 {Omega} sheet resistance. ABout 40 percent of the bits were successfully operated with a {+-} 18-percent bias margin. A minimum 570-ps access time with 13-mW power dissipation was obtained for the highest peripheral circuit bias conditions.

OSTI ID:
7140234
Journal Information:
IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA), Vol. 24:5; ISSN 0018-9200
Country of Publication:
United States
Language:
English