Four-to-two adder cell for parallel multiplication
This patent describes an adder circuit for receiving four input numbers and generating two output numbers that when summed equals the summation of the four input numbers. It comprises: a plurality of adder cells arranged in parallel, each the adder cell for adding corresponding bits of the four imputed numbers. The adder cell comprising: a carry generator circuit coupled to accept three of four corresponding bits from its previous adder cell and coupled to provide an intermediate carry output as a first input to a first multiplexer (MUX) and a complement of the intermediate carry output as a second input to the first MUX; a parity circuit coupled to accept the four corresponding bits of the input numbers for generating a control signal determined by a parity comparison of the four corresponding bits; one of the four corresponding bits which corresponds to a number not coupled to receive a bit from its previous adder cell being coupled as a first input to a second MUX and the complement of the intermediate carry output being coupled as a second input to the second MUX; and the control signal selecting between the first and second inputs to the first MUX for determining one of the two output numbers and the control signal also selecting between the first and second inputs to the second MUX for determining other of the two output numbers.
- Assignee:
- Intel Corp., Santa Clara, CA
- Patent Number(s):
- US 4901270; A
- Application Number:
- PPN: US 7-248797A
- OSTI ID:
- 6991856
- Resource Relation:
- Patent File Date: 23 Sep 1988
- Country of Publication:
- United States
- Language:
- English
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