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Title: A radiation-hardened 10K-gate CMOS gate array

Conference · · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA)
OSTI ID:6948248
; ; ; ;  [1];  [2];  [3]
  1. Toshiba Corp., 1, Komukai-Toshiba-cho, Saiwai-Ku, Kawasaki, 210 (JP)
  2. lwate-Toshiba Electronics Corp., Kitakami, 024 (JP)
  3. TOSNEC, Kawasaki, 210 (JP)

This paper reports a radiation-hardened 10013-gate complementary metal-oxide-semiconductor (CMOS) gate array with a 5-V supply voltage designed and fabricated utilizing Si-gate Epi-CMOS technology with two-level metallization. N-channel metal-oxide-semiconductor (NMOS) and p-channel metal-oxide-semiconductor (PMOS) transistor gate lengths in basic cells are 2 {mu}m. A one hundred krad (Si) total dose radiation hardness has been realized by introducing a thin field oxide between the source/drain diffusion layers and a thick field oxide in NMOS transistors both in the basic cells and I/O cells, and the buried P+ diffusion layer under a poly-Si layer at the P-well edge in the basic cells, without sacrificing speed performance.

OSTI ID:
6948248
Report Number(s):
CONF-890723-; CODEN: IETNA; TRN: 90-014141
Journal Information:
IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA), Vol. 36:6; Conference: 26. annual conference on nuclear and space radiation effects, Marco Island, FL (USA), 25-29 Jul 1989; ISSN 0018-9499
Country of Publication:
United States
Language:
English