Finite-precision arithmetic in singular-value decomposition architectures
The singular-value decomposition (SVD) is an important matrix algorithm that has many applications in signal processing. However, its use has been limited due to its computational complexity. Several architecture have been proposed to compute the SVD using arrays of parallel processors. This thesis derives requirements for the precision of arithmetic units (AUs) used in SVD arrays and compares the resource requirements of several architectures. The author's results are based on the assumption that he is operating on matrices of quantized data. Since the matrices have quantization errors, he shows that their singular values will have quantization errors as large as the data errors. To compute the number of bits needed in SVD AUs, it is required that the AUs have enough bits to keep the round-off errors of the SVD computation smaller than the quantization errors. The analysis shows that we need essentially the same number of bits for either the Hestenes of Jacobi SVD algorithms. Five SVD architectures, two linear structures and three quadratic arrays are described and their resource requirements are compared with floating point and CORDIC AUs. The comparison shows the total resource requirements of the linear designs to be lower than that of the quadratic arrays for all-size matrices.
- Research Organization:
- Cornell Univ., Ithaca, NY (USA)
- OSTI ID:
- 6818788
- Resource Relation:
- Other Information: Thesis (Ph. D.)
- Country of Publication:
- United States
- Language:
- English
Similar Records
Quantifying the Impact of Single Bit Flips on Floating Point Arithmetic
Singular value decomposition utilizing parallel algorithms on graphical processors